Resistive memories of the OxRRAM (Oxide-Based Resistive Random Access Memories) type that typically comprise a layer of metal oxide, are preferentially chosen for non-volatile applications, with the purpose of replacing memories of the Flash type. They in particular have the advantage of being compatible with the end of line method (acronym BEOL for “Back-End Of Line”) of the CMOS technology (acronym for “Complementary Metal-Oxide-Semiconductor”). OxRRAM resistive memories are devices that comprise in particular a layer of metal oxide arranged between two electrodes. The electrical resistance of such devices can be modified by writing and erasing operations. These writing and erasing operations make it possible to switch the OxRAM resistive memory device from a low resistive state (LRS) to a high resistive state (HRS) and inversely.
From cycle to cycle, the resistances of the low resistive LRS and high resistive HRS states do not show very good reproducibility in terms of performance. A variability in cycle-to-cycle performance is indeed observed. This variability is especially substantial for the high resistive state HRS, inducing a decrease in the programming window, and even a total loss of the programming window. This problem of variability is a genuine obstacle for industrialization.
This problem remains despite many efforts made in the fields of methods for creating resistive memory devices and programming methods.
Many studies have been conducted in order to reduce the variability of electrical performance by reducing the dimensions of the memory device. In particular, it has been shown in the publication: “Conductive Filament Control in Highly Scalable Unipolar Resistive Switching Devices for Low-Power and High-density Next Generation Memory”, Kyung-Chang Ryoo et al., IEDM2013, that a solution for reducing the dimensions of the memory device is to reduce the contact surface between one of the electrodes and the oxide layer.
FIG. 1A shows a memory device comprising a metal oxide layer 300 arranged between a first electrode 100 and a second 200 electrode, according to prior art. Conductive filaments 500 are created through the oxide layer 300. It appears that the conductive filaments 500 can be dispersed on the contact surfaces that separate each one of the electrodes 100, 200 from the oxide layer 300. This dispersion of conductive filaments 500 in the oxide layer 300 can be responsible for the variability in performance, observed for resistive memory devices of prior art.
FIG. 1B shows a memory device comprising an oxide layer 300 arranged between a first electrode 100 and a second electrode 200, according to prior art. The device shows a reduced contact surface between the second electrode 200 and the oxide layer 300. It appears that the conductive filaments 500 are directed towards the reduced contact surface.
The disadvantage with this type of memory device is the complexity of the manufacturing method. Indeed, in order to form a reduced contact surface between the second electrode and the oxide layer, it is necessary to carry out many and therefore expensive steps. In particular, the steps of lithography, depositing, planarization, required for obtaining nanometric dimensions on the contact between the electrodes and the dielectric material are complex and require complicated development steps. Moreover, making contact on a small surface inevitably results in additional constraints in terms of industrialization.
This invention makes it possible to resolve all or, at least a portion of the disadvantages of current techniques. It would in particular be advantageous to propose a solution to reduce and even eliminate the variability in performance observed cycle after cycle for resistive memory devices, while still limiting or avoiding the disadvantaged of the manufacturing methods known in prior art mentioned hereinabove.